This invention relates in general to sense amplifier circuits and in particular, to a high-speed sense amplifier circuit operable with low-voltage power sources to provide, on two output data lines, a first and a second complementary latched logic level data output indicative of a voltage difference between two input data lines.
FIGS. 1A and 1B respectively illustrate, as examples, a conventional latched sense amplifier circuit 2, and a block diagram of a sensing circuit 1 which includes the latched sense amplifier circuit 2. The sense amplifier circuit 2 generates complementary data outputs, dout1' and dout2', which are indicative of a differential voltage between two data inputs, din1 and din2, received by the sense amplifier circuit 2. The output voltages, dout1' and dout2', generated by the sense amplifier circuit 2 generally do not reach full-swing (i.e., the HIGH output does not reach Vdd, and the LOW output does not reach GND), because the differential voltage received by the sense amplifier circuit 2 is typically too small. Accordingly, the sensing circuit 1 also includes a latching circuit 3 which generates latched logic level outputs, dout1 and dout2, by pulling the data outputs, dout1' and dout2', up to their respective full-swing or logic level values, and holding them there.
One problem with the sensing circuit 1 of FIG. 1b, is that the latching circuit 3 introduces a delay which reduces the overall performance of the sensing circuit 1. Another problem is that dc power dissipation frequently is unavoidable in such designs. Still another problem is that such designs frequently perform poorly when operated with low voltage sources such as batteries.